An example of a conventional non-volatile inverter appears in U.S. Pat. No. 5,587,603 and is hereby incorporated by reference in its entirety. The '603 patent highlights the use of a single floating poly gate/layer to drive a P-channel transistor and an N-channel transistor of an inverter latch. The floating poly also needs a third terminal connected to provide an ERASE function.
In U.S. Pat. No. 4,829,203 (also incorporated by reference in its entirety), a single floating poly gate/structure controls both P-channel and N-channel devices of the inverter latch for an integrated programmable bit. The design appears to be complex, with the implementation of an additional diode and pullup transistor. U.S. Pat. No. 4,885,719 (also incorporated by reference in its entirety) is similar to the '203 and '603 schemes and has a shared floating gate.
None of the above-discussed schemes appears appropriate for SONOS (silicon-oxide-nitride-oxide-silicon) technology, since conducting floating gates appear to be required. Conventional technology does not appear to benefit from control of the supply busses (e.g., varying or changing supply voltages in a controlled manner).